Formal Verification Engineer

Role Summary

• We are looking for a Formal Verification Engineer to join our team in Haifa, Israel.
• You will be responsible for verifying the correctness of complex digital designs using formal methods.

Responsibilities

• Develop and implement formal verification methodologies.
• Create and maintain verification plans and testbenches.
• Collaborate with design teams to identify verification requirements.
• Analyze and debug design issues found during verification.
• Provide feedback and recommendations for design improvements.

Requirements

• Bachelor's or Master's degree in Computer Science, Electrical Engineering, or related field.
• Experience with formal verification tools and methodologies.
• Strong knowledge of digital design and verification concepts.
• Proficiency in programming languages such as SystemVerilog, C++, or Python.
• Excellent problem-solving skills and attention to detail.
• Ability to work collaboratively in a team environment.

Department

• Engineering

Job Type

• Full-time